A DRAM cell consists of a transistor having a drain-source passage connected between a bit line and a cell node, and a storage capacitor connected between the cell node and a cell plate. As the memory density of the DRAM is increased, the area occupied by the DRAM cell is proportionately reduced. Accordingly, the capacitance of the storage capacitor is decreased. Therefore, in an attempt to maximize the capacitance of the storage capacitor, three dimensional DRAM cells such as those having a trenched structure or a stacked structure have been developed. The storage capacitor in the trenched structure is formed in a groove in the semiconductor substrate; the stacked storage capacitor in the stacked structure is stacked upon the semiconductor substrate.
The stacked capacitor type DRAM cell is manufactured by stacking the capacitor upon the semiconductor substrate; therefore, it is advantageous in that it can be manufactured more easily than the trenched capacitor type DRAM cell. Furthermore, the stacked capacitor type DRAM cell does not have electrical problems such as punch-through and current leakage between a trenches and a trench, which are present in the trenched capacitor type DRAM cell.
FIG. 1 is a vertical sectional view of a conventional stacked type DRAM cell. The construction of this conventional stacked type DRAM cell will be briefly described below.
A P type well 2 is formed upon a P type substrate 1. A field oxide layer 4 is formed to isolate or to separate the memory cells from each. A P.sup.+ channel stopper layer 3 is formed under the field oxide layer 4. Thereafter, a gate oxide layer 5 is formed, and an N.sup.+ impurity doped polycrystalline silicon layer 6, which is to serve as a gate electrode of a switching transistor is formed on the gate oxide layer 5. Then, on the field oxide layer 4, a polycrystalline silicon layer 7 which is to serve as a gate electrode of an adjacent memory cell. Then, an N.sup.+ source region 8 and an N.sup.+ drain region 9 of the switching transistor are formed, and an insulating layer 11 is formed to insulate the polycrystalline silicon layers 6,7.
Then, an N.sup.+ doped polycrystalline silicon layer 12 which is to serve as an electrode of the storage capacitor is formed on the insulating layer 11 such that it overlaps the polycrystalline silicon layers 6,7, and also contacts a portion of the source region 8.
The dielectric layer 13 of the storage capacitor is formed on the surface of the polycrystalline silicon layer 12. On the dielectric layer 13, an N.sup.+ doped polycrystalline silicon layer 14 is formed to serve as another electrode of the storage capacitor is formed. An insulating layer 15 is formed upon the polycrystalline layer 14. On the insulating layer 15, a conductive layer 16 is formed to serve as a bit line, which also contacts the drain region 9.
In such a conventional stacked capacitor type cell structure, the cell area is reduced as the density of the DRAM memory is increased; therefore, the capacitance of the capacitor would be decreased. Consequently, the density of this conventional stacked capacitor type DRAM cell is confined to the order of 4M. Accordingly, if the ultra high integration DRAM cells of 16M or 64M are to be realized, the capacitance of the capacitor has to be increased. In an effort to provide a solution to that problem, brisk research is ongoing in the relevant field.